Verilog Design

Serial to Parallel Data Conversion

A serial to parallel data conversion requires n-bit shift register. Therefore, a serial-in/parallel-out shift register converts data from serialformat to parallel format. If four data bits are shifted in by four clock pulses via a single wire at serial-in, the data becomes available simultaneously on the four outputs parallel_out[3] to parallel_out[0] after the fourth clock pulse.

A serial to parallel data conversion circuit is used for converting a serial word supplied by some domain "X" to a parallel word so as to allow for the processing of the parallel word by a processor. The "X" domain supplies to the interface circuit a 'ready' pulse signal. The interface circuit, in response to the 'ready' pulse signal, supplies an 'ack' pulse and a 'clock' signal to the "X", so as to allow the serial word from the "X" to be transferred to the interface circuit, which then converts the serial word to a parallel word. An enable pulse signal supplied to the interface circuit effects the transfer of the parallel word from the interface circuit to the processor. 

module serial_2_parallel (
clk_in,
rst_n,
ready_in,
shift_enable,
serial_in,
ack_out,
parallel_out );

// I/O declarations

input clk_in;
input rst_n;
input ready_in;
input shift_enable;
input serial_in;

output [3:0] parallel_out;
reg [3:0] parallel_out;
output ack_out;
reg ack_out;

wire [3:0] parallel_wire;

// A 4-bit shift register to convert serial to parallel

always@(posedge clk_in or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
parallel_out <= 4'b0;
ack_out <= 1'b0; // ack_out is initially 0
end
// Shift enable is driven from tb as 1 when ack_out is 1
else if (shift_enable == 1'b1 && ready_in == 1'b1)
parallel_out <= ({serial_in, parallel_wire[3:1]});
else
begin
parallel_out <= parallel_wire;
ack_out <= 1'b1;
end
end 

// Declare a 4-bit wire

assign parallel_wire = parallel_out;

endmodule

Gray Code Counter Implementation

A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. The term Gray code is often used to refer to a Binary Reflected Gray Code. We can implement a gray code counter in a different ways. Consider the following table carefully.

B : 000, 001, 010, 011, 100, 101, 110, 111
G: 000, 001, 011, 010, 110, 111, 101, 100

To convert a binary number d1,d2,..,d(n-1),dn to its corresponding Binary Reflected Gray Code, start at the right with the digit dn (the LSB). If the d(n-1) is 1, replace dn by (1-dn); otherwise, leave it unchanged. Then proceed to d(n-1). Continue up to the first d1, which is kept the same. The resulting number g1,g2,..,g(n-1),gn is the Reflected Binary Gray Code. 

The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted. We illustrate the 3-bit binary Gray code as an example.

Binary to gray code can be achieved by

gray[2] = binary[2];

gray[1] = binary[2] ^ binary[1];

gray[0] = binary[1] ^ binary[0];

A simple verilog code to implement this function is given by

assign gray = (binary>> 1) ^ binary; // Right shift by 1 and EX-OR with binary.

 module gray_cntr (  
     clock_in,     rst_n,     enable_in,
     cnt_out
    );
    
    // I/O Declarations
    input clock_in, rst_n, enable_in; 
    output [ 2:0] cnt_out;
    wire [2:0] cnt_out;
    reg [2:0] cnt;
    
    always @ (posedge clock_in or negedge rst_n) 
    if (!rst_n) 
      cnt <= 1'b0; 
    else if (enable_in) 
      cnt <= cnt + 1'b1; 
      
    assign cnt_out = { cnt[2], (^cnt[2:1]), (^cnt[1:0]) };
      
  endmodule